1. Field of the Invention
The present invention relates to manufacturing masks for the formation of semiconductor substrates and ceramic interconnect packaging substrates, in particular, to methods of making fine geometrical dimension masks for deposition of electrically conductive materials on preselected areas of the substrates.
2. Description of Related Art
In the formation of integrated circuits, masks are used for forming electrically conductive features on a semiconductor substrate or in Integrated Circuit (IC) packaging. A mask is a layer of material having openings or vias therein, whereby the mask is held over at least one surface of the substrate for forming these electrically conductive features on the substrate surface. These openings or vias in the mask define a desired circuit, IC package or other conductive surface features.
Masks are commonly used for sputter, evaporative deposition or screening of a conductive material within features created in the mask corresponding to preselected areas of the substrates. For instance, masks may be used to form input/output (I/O) sites or conductive lines on the substrate surface. In formation of I/O sites, the mask is typically an evaporation mask whereby conductive material is sputter or evaporative deposited within features in the mask corresponding to sites on the substrate where such I/O sites are to be formed. A conductive metal layer is often sputtered or evaporated within these openings or vias to form electrically conductive solder bump flip chip connections, such as controlled-collapse chip connections (C4). In the formation of conductive lines, a conductive material, such as a conductive paste, is screened within features in the mask corresponding to sites on the substrate where these lines are to be formed. Typically, these conductive pastes are screened into the openings in the mask to form multi-layer ceramic (MLC) packages.
Yet, in accordance with current semiconductor technology, the methods of forming such masks, and the resultant masks formed, are limited in both size and feature dimensions of the openings or vias formed therein. That is, current technology sets dimensional limits on the achievable geometrical dimensions of electrically conductive features formed within current technology masks that enable the production of effective and efficient semiconductor technology and IC packaging.
As semiconductor technology continues to proliferate, future generations of smaller, faster semiconductor technology and IC packaging will require masks imaged with smaller and denser features that will enable the achievement of these future generations of technology.
In view of the foregoing, a need therefore exists in the art to provide improved masks having significantly reduced geometrical dimensions for forming electrically conductive features within such masks that will accommodate future generations of semiconductors or integrated circuits.